I2C - Master write v1
I2C - Master write v1 — The I2C Master write driver
block allows data to be written to a device supporting the I2C slave protocol.
One block is required for each channel to be written. Multi-master mode and
clock stretching are currently not supported.
Library
Simulink Real-Time - Speedgoat
Description
The I2C Master write driver block allows data to be written to a device supporting
the I2C slave protocol.
One block is required for each channel to be written. Multi-master mode and clock
stretching are currently not supported.
Ports
This driver block has three inputs port.
Inputs
-
Slave ID
7-bit identifier to access the I2C Slave node.
-
Number of Bytes to Write
Defines the number of bytes to write, meaning the number of data
vector elements that are transmitted. This value must be between 0 and
256.
-
Data
Vector of data to transmit. The vector size is 256. Each element of
the vector represents one byte. Values between 0 and 255 are allowed.
The number of bytes written to the bus is defined in the Number of Bytes to Write parameter, starting
from the first element of the vector. Unused elements of the vector are
ignored.
Outputs
-
Ack Error
Displays the error flag related to I2C acknowledge. This port is only
available when the Show Acknowledge Error
Port parameter is enabled.
Parameters
Tab: Module setup
-
Configurable I/O Module ID
This parameter associates a code module block with a configurable I/O module setup
block. Set this value to match the Module ID defined in the setup block of the
required configurable I/O module.
-
Channel
The number of the channel which this driver block entity will access. Only one
channel per driver block can be addressed. You can specify channels in the range 1-N
(N = the number of channels implemented in your specific configuration file defined
in the Setup block).
-
Sample Time
Defines the base sample time at which this driver block gets its sample hit. This
parameter can also be set to -1 for inherited
sample time. The units are in seconds.
Tab: I2CM
-
I2C Clock Rate
Configures the I2C transmission clock rate. When selecting Custom, any rate between
fFPGA/8 and fFPGA/
(216 − 1) can be specified. The rate is
derived from the FPGA frequency using a clock divider; therefore, exact
rates across the full specified range cannot always be achieved. The
effective rate and the corresponding relative error are
displayed.
Example: If the FPGA frequency is 75 MHz, then the corresponding
frequency range is approximately 9.375 MHz to 1.144 kHz.
-
Show Acknowledge Error Port
By checking this parameter, an additional output becomes available
which indicates the status of the acknowledge flag (1: error, 0: no
error).
-
Read Value From Previous Model Step
This parameter is only visible if Show
Acknowledge Error Port is selected. By checking this
parameter, the driver output Ack Error
contains the I2C ack error state from the previous model step. This
option reduces the TET. Otherwise, the driver actively waits for the I2C
transfer (which increases the TET) to be finished and then the output
Ack Error contains the I2C ack
error state from the current model step.