Documentation

This parameter associates a code module block with a configurable I/O module setup block. Set this value to match the Module ID defined in the setup block of the required configurable I/O module.

A vector of channels this driver block entity will access. You can specify channels in the range 1-N (N = the number of channels implemented in your specific configuration file defined in the Setup block). The width of this vector also defines the subsequent size of some of the following parameters if scalar expansion applies. With a single block, all the channels of the block are synchronized.

This parameter defines the required bit rate, expressed in bits per second.

	Note
	The accuracy of the effective bit rate can vary depending on the FPGA frequency defined in the configuration file. The effective bit rate and the relative error are shown in the block mask.

This field shows the effective bit rate computed based on the I/O module performance.

The effective bit rate will always be an integer division of the I/O module frequency, which can be verified in the IO3xx Setup block mask. When selecting higher bit rates, do not overlook the steps between the possible bit rates. Refer to the table below for the fastest rates available.

The effective bitrate can be calculated using this formula:

bitrate_effective = (fpga_frequency/clock_divider) / 2;

The following table shows the possible bitrates for configuration files with 75 MHz and 100 MHz I/O module frequencies:

This field shows the variation between the defined bit rate and the effective bit rate. The units are in percentiles. For instance: 0.16 means 0.16%.

From the list, choose - None - Even - Odd - Mark - Space. This parameter defines the receive and transfer parity.

This parameter defines the data length in bits of the UART word. Correct values are in the range 5 to 9.

This parameter defines how many stop bits are used by the protocol. Correct values are in the range 1 to 2.

The value 1 in this vector enables the half duplex mode: The physical Tx line of the affected channel turns into Dx (Data Pin). This means that the Tx line is only actively driving the Tx signal when there are Tx data to be sent. When there are no Tx data to be sent (after the end of each Tx frame), the Tx line is not actively driven anymore and switches over to an Rx line. The physical Rx line becomes unnecessary in that case and can be left unconnected.

The value 0 means that the Tx line is constantly driven and therefore, full duplex with separated Tx and Rx lines is used (default case).

This parameter defines the duration after which a character timeout is detected. The unit is in UART words. For example, a value of 1 would trigger a timeout interrupt at the end of a frame if one word is missing. A value of 0 disables the character timeout. With the Serial Interrupt source Speedgoat IO3xx Serial in combination with the Read Character Timeout Status v1 driver block, a subsystem or a complete model can be triggered by the Rx Character Timeout.

	Note
	Additional important information is available in the IO3xx Serial - Loopback Interrupt example.