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v10.0.1.x for R2026a
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SPI - Master / Slave v2

SPI - Master / Slave v2 — The SPI driver block can act as SPI Master or SPI slave.

Library

Simulink Real-Time - Speedgoat

Description

The SPI driver block can act as SPI Master or SPI slave.

Ports

Inputs
Tx Data n (n is the channel number)

The data of this input signal are transferred within the next available SPI frame.

Outputs
Rx Data n (n is the channel number)

This output signal represents the data of the last frame received.

Rx Data n valid (n is the channel number)

This output indicates that a complete SPI frame has been received and all Rx Data n are valid. This output is not visible if the SPI mode is master and Sync Mode is set.

[Note]Note

The number of vector elements of Tx Data n and Rx Data n is defined with the frame size parameter in the SPI configuration tab. Each element of the data vector corresponds to a SPI data word.

Parameters

Tab: Module setup
Configurable I/O Module ID

This parameter associates a code module block with a configurable I/O module setup block. Set this value to match the Module ID defined in the setup block of the required configurable I/O module.

Channel Vector

A vector of channels this driver block entity will access. You can specify channels in the range 1-N (N = the number of channels implemented in your specific configuration file defined in the Setup block). The width of this vector also defines the subsequent size of some of the following parameters if scalar expansion applies. With a single block, all the channels of the block are synchronized.

Sample Time

Defines the base sample time at which this driver block gets its sample hit. This parameter can also be set to -1 for inherited sample time. The units are in seconds.

Tab: SPI Configuration
Role

SPI role, there are two possibilities:

  • Master

In this case, the SPI block controls the SPI data transfer. It initiates frame starts and defines all frame parameters.

  • Slave

In this case, the SPI block receives and transmits its data depending on the incoming SPI frame.

Sync Mode

This parameter is only available when Role is set to master.

When set, the SPI block starts a new frame when the simulation step begins and actively waits until the complete SPI frame is transferred. Note that the CPU is blocked for at least the complete SPI frame time (for details see SPI Transfer Timing with synchronized Master)

Multislave Mode

This parameter is only available when Role is set to master.

When set, the SPI master can communicate with up to 8 different slaves using multiple chip selection signals.

[Note]Note

The Channel Vector is limited to one element in multislave mode. One driver block cannot contain more than one SPI master that is running in multislave mode. All the scalar expandable parameters described below will be used for the frame settings of each multislave channel.

Multislave Channel Vector

This parameter is only available when Role is set to master and Multislave Mode is set.

A vector of slave channels that is accessed by this master driver block. You can specify channels in the range 1-8. The width of this vector also defines the subsequent size of some of the following parameters if scalar expansion applies. The order of these channels corresponds to the order of the SPI frames sent to the different slaves.

Write Tx Data Only

When set, there will be no Rx Data n output signals.

Read Rx Data Only

This parameter is only available when Role is set to slave.

When set, there will be no Tx Data n input signals.

CPOL Vector

The clock polarity parameter (for details see CPOL and CPHA):

  • 0: SCLK idle state is low

  • 1: SCLK idle state is high

CPHA Vector

The clock phase parameter (for details see CPOL and CPHA):

  • 0: sample on the leading (first) clock edge regardless of whether the first clock is rising or falling

  • 1: sample on the trailing (second) clock edge regardless of whether the second clock is rising or falling

Transmission Frequency Vector [Hz]

This parameter is only available when Role is set to master.

This parameter defines the clock rate of the serial clock I/O line.

[Note]Note

The frequency actually applied is always an integer fraction of the FPGA frequency. For example, if the FPGA frequency is 75 MHz and the desired frequency is 510 kHz, the closest possible frequency of 75 MHz/147 = 510.2041 kHz will be applied.

Start Delay Vector [s]

This parameter is only available when Role is set to master.

The time between the activaction of the chip select I/O line and the first applied edge of the serial clock I/O line (for details see Timing Diagram)

Interword Delay Vector [s]

This parameter is only available when Role is set to master.

Idle time between words of a single frame (for details see Timing Diagram)

Stop Delay Vector [s]

This parameter is only available when Role is set to master.

The time between the last applied edge of the serial clock I/O line and the deactivaction of the chip select I/O line (for details see Timing Diagram)

Delay Compensation Vector [s]

This parameter is only available when Role is set to master.

The time to compensate the signal delay which is the sum of the:

  • Delay of the master clock I/O line output to the slave clock I/O line input

  • Delay of the slave clock I/O line input to the slave serial I/O line output (slave data processing delay)

  • Delay of the slave serial I/O line output to the master serial I/O line input

For details see Timing Diagram

Words per Frame Vector

Defines the number of words per frame. The range of this parameter depends upon the SPI mode:

  • Master Synchronized: Valid range is 1 to 1024. With this setting, the number of words sent within one frame can be controlled with an input signal when the Make dynamic checkbox is enabled. Note that the Words per Frame Vector parameter still defines the maximum possible frame size.

  • Master Non-Synchronized: Valid range is 1 to 512

  • Slave: Valid range is 1 to 256

Bits per Word Vector

Defines the number of bits per word. Valid range is 1 to 32

[Note]Note

The signals Tx Data n and Rx Data n are uint32 values. The number of bits that are packed into a SPI data word is always right-aligned (least significant bits are used).

Transmit LSbit first Vector

Defines the order of the bits being transferred.

  • 0: The least significant bit is transmitted as the last bit within a single SPI word

  • 1: The least significant bit is transmitted as the first bit within a single SPI word

No Chip Select

This parameter is only available when Role is set to slave.

When activated, the slave ignores the chip select I/O line. Instead, a frame start is detected with the first detected edge on the clock I/O line and a frame end occurs when the clock I/O line is idle for a time greater than Clock Timeout.

[Note]Note

When No Chip Select is set and Write Tx Data Only is not set, CPHA must be set to 1. (for details see SPI Transfer without chip select)

Clock Timeout Vector

This parameter is only available when Role is set to slave and No Chip Select is set.

If the clock I/O line was inactive for this time (no signal edges detected), the present SPI frame is finished.

Data Sync Length Vector

This parameter is only available when Role is set to master and if the configuration file supports SPI v2.7 or newer.

Defines the length in seconds of the physical SYNC signal of the SPI unit.

Generate Data Sync at Frame Start Vector

This parameter is only available when Role is set to master and if the configuration file supports SPI v2.7 or newer.

Defines the behavior of the physical SYNC signal of the SPI unit at frame start.

  • 0: No pulse is generated at SPI frame start on the physical SYNC signal

  • 1: A pulse is generated at SPI frame start on the phsyical SYNC signal

[Note]Note

The FPGA clock frequency and the corresponding time of a tick can be found in the Setup block.