Documentation

The number of ticks during which the signal was high between two triggering events.

The number of ticks during which the signal was low between two triggering events.

This output returns the number of ticks counted between two triggering events.

This output returns the duty cycle coded on 16 bits. The range is between 0.0 and 1.0 (only visible if the configuration file supports duty cycle calculations).

This output returns the duty cycle coded on 8 bits. The range is between 0.0 and 1.0 (only visible if the configuration file supports duty cycle calculations).

This output returns the number of ticks counted between a triggering event and the rising edge of the input signal (only visible if the configuration file supports PWM Capture v1.2 or newer).

This output returns the number of ticks counted between a triggering event and the falling edge of the input signal (only visible if the configuration file supports PWM Capture v1.2 or newer).

This output returns true when two triggering events occur before the timeout duration (only visible if the configuration file supports PWM Capture v1.2 or newer).

This parameter associates a code module block with a configurable I/O module setup block. Set this value to match the Module ID defined in the setup block of the required configurable I/O module.

A vector of channels this driver block entity will access. You can specify channels in the range 1-N (N = the number of channels implemented in your specific configuration file defined in the Setup block). The width of this vector also defines the subsequent size of some of the following parameters if scalar expansion applies. With a single block, all the channels of the block are synchronized.

Defines the base sample time at which this driver block gets its sample hit. This parameter can also be set to -1 for inherited sample time. The units are in seconds.

Defines the nature of a trigger event. Four modes are available:

Each rising edge of the input signal generates a trigger event

Each falling edge of the input signal generates a trigger event

Each rising edge of the additional trigger input signal generates a trigger event

A trigger event is generated with every model step

When Capture mode is set to High Transitions Triggered or Low Transitions Triggered, the absence of transitions for a duration greater than the Capture Timeout Vector will cause the PWM Capture to initiate an internal trigger. Correct values are in the range 0 to 223 ms. When the Capture Timeout Vector is set to 0, the feature is disabled. The parameter is only visible if the configuration file supports PWM Capture v1.2 or newer.

Defines the time in seconds during which the input and the trigger input signal must be stable before an edge is detected. Defaults to 100e-9 (100 ns).

The range and resolution of the debounce duration depend on the module frequency that is shown in the Setup block. The Effective Debounce Time therefore indicates the applied duration at the module level.

To disable debouncing, enter the value 0.

Correct values are in the range 0 to 2^18-1 ticks (e.g., 3.495 ms at a frequency of 75 MHz). The parameter is only visible if the configuration file supports PWM Capture v1.12 or newer. The parameter must be a scalar value that applies to all channels defined in the Channel Vector.

When this parameter is checked an additional output is available to read the high duration of the recorded signal between two trigger events.

When this parameter is checked an additional output is available to read the low duration of the recorded signal between two trigger events.

When this parameter is checked an additional output is available to read the total duration between two trigger events.

When this parameter is checked an additional output is available to read the duty cycle computed by the configurable I/O module and coded on 16 bits. The module will compute the ratio between high duration and the period. The duty cycle is encoded between 0.0 and 1.0 with an accuracy of 2^-15. Compared to duty cycle computation within Simulink, one PCI access is saved. When more than one channel is selected and if these channels are contiguous, the PCI read access is packed. Two CAP channels can be read in one PCI access. The parameter is only visible if the configuration file supports duty cycle calculations.

When this parameter is checked an additional output is available to read the duty cycle computed by the configurable I/O module and coded on 8 bits. The module will compute the ratio between high duration and the period. The duty cycle is encoded between 0.0 and 1.0 with an accuracy of 2^-7. Compared to duty cycle computation within Simulink, one PCI access is saved. When more than one channel is selected and if these channels are contiguous, the PCI read access is packed. Four CAP channels can be read in one PCI access. This is the suggested option if maximum performance is required (Minimum I/O latency). The parameter is only visible if the configuration file supports duty cycle calculations.

When this parameter is checked an additional output is available to read the time (in ticks) between a trigger event and the rising edge of the input signal. The parameter is only visible if the configuration file supports PWM Capture v1.2 or newer.

When this parameter is checked an additional output is available to read the time (in ticks) between a trigger event and the falling edge of the input signal. The parameter is only visible if the configuration file supports PWM Capture v1.2 or newer.

When this parameter is checked an additional output is available to read the Valid Data Flag. Data Flag is true when the PWM input is captured within the timeout duration. The parameter is only visible if the configuration file supports PWM Capture v1.2 or newer.