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v10.0.1.x for R2026a
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IO421 - Synchro/Resolver Write

IO421 - Synchro/Resolver Write — Writes the IO421 Synchro/Resolver outputs

Library

Simulink Real-Time - Speedgoat

Description

The IO421-4 sub-module simulates up to three Synchro or Resolver. Each simulated device consists of a primary coil, which requires a reference alternating current.The Synchro contains three and the Resolver two secondary coils. The output voltages of the secondary coils depend on the position of the primary coil. You can define the position in the Simulink model, using the S/R write driver block.

The characteristics of the sub-module depend on the factory configuration selected at the time of the order. This information is available in a separate documentation shipped with the device.

sub-module codeFormatOutput (VLL)[VRMS]Ref (VREF)[VRMS]Frequency [Hz]Max Load [VA]
60SYN2 - 11.82 - 28360 - 1k0.25
61RSL2 - 11.82 - 28360 - 1k0.25
63SYN9010 - 115360 - 1k0.25
64RSL9010 - 115360 - 1k0.25
65SYN11.82 - 2847 - 4000.25
66RSL2 - 11.82 - 2847 - 4000.25
68SYN9010 - 11547 - 4000.25
69RSL9010 - 11547 - 4000.25
6ARSL2 - 11.82 - 281k - 3k0.25
6BRSL2 - 11.82 - 283k - 5k0.25
6CRSL2 - 11.82 - 285k - 7k0.25
6DRSL2 - 11.82 - 287k - 10k0.25
6JSYN2 - 11.82 - 281k - 3k0.25
6KSYN2 - 11.82 - 283k - 5k0.25
6LSYN2 - 11.82 - 285k - 7k0.25
6MSYN2 - 11.82 - 287k - 10k0.25
6TSYN2 - 11.810 - 11547 - 4000.25
6USYN2 - 11.810 - 115360 - 1k0.25

Ports

Inputs
rotation rate

The required rotation velocity of the shaft. This port is only enabled when the Rotation mode parameter is set to either 'Speed driven' or 'Start and stop'. [RPS] (revolutions per second)

start angle

The required shaft angle at the beginning of the sequence. This port is only enabled when the Rotation mode parameter is set to 'Start and stop'. [Radians]

stop angle

The required shaft angle at the end of the sequence. This port is only enabled when the Rotation mode parameter is set to 'Start and stop'. [Radians]

angle

The required shaft angle to be simulated. This port is only enabled when the Rotation mode parameter is set to 'Angle driven'. [Radians]

All ports are vectors combining all used channels. The vector's width and the channel number sequence are defined by the Channel vector parameter.

Parameters

Module ID

The Module ID has two functions:

  • It defines the logical connection between the Setup block and its I/O blocks

  • It also informs the auto-search feature of the PCI Slot parameter. If only one I/O module of this type is installed, the Module ID must be set to 1. If n modules are installed, it must be in the range 1:n. Not all the I/O modules installed in the target machine need to be used. To see how each I/O module maps to a Module ID, use this Speedgoat API: 

    speedgoat.getIoInterfaces("TargetName", "mySpeedgoat")
Slot

The carrier board can contain up to three modules. This parameter indicates where your IO421-4 sub-module is located on the IO421 motherboard.

Channels vector

Enter the channels to be enabled. A correct value is a scalar (if only one channel is used) or a vector with the channel numbers 1 to 3 in any order.

Expected excitation voltage VREF vector (RMS)

In ratio-metric mode this parameter and VLL output level vector define the gain for the maximum VLL output level: Gain = VLL output level / Expected excitation voltage In fixed mode, this is the assumed constant excitation voltage level, so the output doesn't depend on the amplitude of the applied excitation voltage. Still, the frequency of the output signals is taken from the applied excitation. Units are V RMS.

[Note]Note

The phase lock between the excitation and the signal output can take up to 1 second after connecting a valid excitation signal or starting the model. Consequently, no signals are immediately present at the output.

VLL output voltage vector (RMS)

This parameter defines the output amplitude of the synchro or resolver simulation output depending on the Output mode. Units are V RMS.

Two-speed mode

The channels 1 and 2 can be configured to work together in a two-speed mode. Setting an integer greater than '1', channel 2 will output the signal of channel 1 divided by that integer. See Synchro/Resolver connections for an example. configuration The maximum divider value is 255. Set '1' to deactivate this function and use channel 2 independently.

Output mode

The representation of the output value. Options are:

  • Ratio-metric: The output amplitudes are based on the amplitude of the reference voltage input divided by the ratio VLL output voltage / Expected excitation voltage. VOUT = VREF IN * (VLL output voltage / Expected excitation voltage)

  • Fixed: The output amplitudes are based on the VLL output level vector parameter.

Rotation mode

The simulation method. Options are:

  • Velocity driven: the output is continuously updated depending on the value of the 'rotation rate' input port.

  • Start and stop: the output is first set to the angle in the 'start angle' input port, then changes at the speed applied to the 'rotation rate' input port to the angle in the 'stop angle' input port.

  • Angle driven: the output is continuously updated depending on the value of the 'angle' input port.

Output format

Output format

  • Synchro

  • Resolver

Phase offset vector [°]

The phase of each individual channel's outputs may be offset from reference input. The phase may be adjusted between -90° and 90° with a resolution of 0.1°.

Sample Time

Defines the base sample time at which this driver block gets its sample hit. This parameter can also be set to -1 for inherited sample time. The units are in seconds.

PCI Slot (-1: auto-search)

There are two approaches for mapping this block to a specific I/O module installed in your target machine. All modules of the same type must be configured using the same method.

  • Auto-Search: with the default value -1 the I/O module will be automatically located in the target machine. If you have multiple modules of the same kind, the Module ID defines which module is associated with this block. To see how each I/O module maps to a Module ID, use this Speedgoat API: 

    speedgoat.getIoInterfaces("TargetName", "mySpeedgoat")

  • Explicit Addressing: to explicitly define the logical address of the I/O module in the target machine, you can provide the PCI bus and slot numbers as a vector: [bus, slot]. To determine these numbers, run the following command in the MATLAB command window: 

    speedgoat.getIoInterfaces("TargetName", "mySpeedgoat", "Advanced", true)

    Note that the PCI address can change whenever an I/O module is added or removed – usually, auto-search is the best option.