Documentation search search close
CONTENTS
https://www.speedgoat.com/help/slrt/page/icon_documentation.jpg
v10.0.1.x for R2026a
View other versions

BiSS - Sniffer v2

BiSS - Sniffer v2 — The BiSS Sniffer code module is used to monitor the data stream of an existing BiSS data communication. The current implementation is intended to be generic and can capture up to 64-bits of data.

Library

Simulink Real-Time - Speedgoat

Description

The BiSS Sniffer code module is used to monitor the data stream of an existing BiSS data communication. The current implementation is intended to be generic and can capture up to 64-bits of data.

The following sections describe the code module in more detail:

  • Usage notes

  • Input and output ports

  • Dialog fields

Ports

The driver has three outputs port and no input ports.

Outputs
RX (63:32)

This output returns up to 32-bits of data. Data is captured MSB first. In a frame of 64-bits, bit 63 corresponds to the first bit of the transmission.

RX (31:0)

This output returns up to 32-bits of data. Data is captured MSB first. In a frame of 64-bits, bit 0 corresponds to the last bit of the transmission.

Number of Bits

This output returns the number of bits that the BiSS Sniffer Code Module captured between the start condition and the timeout event.

The output width is defined by the channel count parameter.

Parameters

Tab: Module setup
Configurable I/O Module ID

This parameter associates a code module block with a configurable I/O module setup block. Set this value to match the Module ID defined in the setup block of the required configurable I/O module.

Channel Vector

A vector of channels this driver block entity will access. You can specify channels in the range 1-N (N = the number of channels implemented in your specific configuration file defined in the Setup block). The width of this vector also defines the subsequent size of some of the following parameters if scalar expansion applies. With a single block, all the channels of the block are synchronized.

Sample Time

Defines the base sample time at which this driver block gets its sample hit. This parameter can also be set to -1 for inherited sample time. The units are in seconds.

Tab: BiSS Sniffer configuration
Timeout vector

The timeout to abort the current communication in case insufficient master clock cycles are received. Units are in ticks, Range 0 to 65535

Line delay compensation vector

The line delay compensation vector intends to compensate. Units are in ticks. Range 0 to 255

[Note]Note

The FPGA clock frequency and the corresponding time of a tick can be found in the Setup block.