Documentation

The data value received from the encoder.

The value of the BiSS CRC Bits specified in the configuration.

The value of the BiSS Warning Flag.

The value of the BiSS Error Flag.

Indicates whether the BiSS data transmission was successful (0) or corrupted (1).

This parameter associates a code module block with a configurable I/O module setup block. Set this value to match the Module ID defined in the setup block of the required configurable I/O module.

A vector of channels this driver block entity will access. You can specify channels in the range 1-N (N = the number of channels implemented in your specific configuration file defined in the Setup block). The width of this vector also defines the subsequent size of some of the following parameters if scalar expansion applies. With a single block, all the channels of the block are synchronized.

Defines the base sample time at which this driver block gets its sample hit. This parameter can also be set to -1 for inherited sample time. The units are in seconds.

Configures the BiSS transmission clock rate in FPGA clock ticks; for example, if we define a value of [10], the clock line will be low for 10 ticks, and high for 10 ticks. The valid range is 6 to 468.

Example: FPGA frequency is 75MHz the corresponding frequency range is approximately 6.25MHz to 80kHz.

Configures the maximum permitted BiSS timeout time. After the last rising edge on the clock line, the BiSS Decoder waits for the configured timeout time before a new transmission can start. During the timeout time, the connected BiSS Encoder must go to idle state (rising edge on SLO).

The same timeout time is used to detect a timeout on SLO, for example when the BiSS Encoder does not respond. If a timeout occurs, the Show Transmission Error output will go high.

Common times are set to 40 us, which corresponds to 3000 ticks @ 75 MHz FPGA frequency.

The number of BiSS data bits. Additional transmission bits such as Warning, Error and CRC are configured separately. The valid range is 0 to a maximum of 64 (the maximum depends on the additional flag and crc port settings).

Configures an Error Flag port.

Configures a Warning Flag port.

Configures the CRC Bits port.

Configures the number of CRC Bits. The valid range is 0 to 8.

If checked, the Transmission Error port is enabled. This port will indicate (1) if an error occurred during the BiSS data transmission (either timeout or corrupt frame).

If checked, the BiSS communication is fully synchronized. This means that in the same sample step the BiSS Decoder starts the communication and actively waits until all data is received. When unchecked, the BiSS Decoder does not wait until the end of the communication. It reads the last valid value (the first value after startup will be invalid). This can help reduce the task execution time.