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v10.0.1.x for R2026a
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IO512 - HDLC/SDLC Setup v4

IO512 - HDLC/SDLC Setup v4 — Setup of parameters for serial ports

Library

Simulink Real-Time - Speedgoat

Description

Your model can contain only one Setup block for each I/O module in your target machine.

Ports

This driver block has no input or output ports.

Block Parameters

Main Tab
Module ID

The Module ID has two functions:

  • It defines the logical connection between the Setup block and its I/O blocks

  • It also informs the auto-search feature of the PCI Slot parameter. If only one I/O module of this type is installed, the Module ID must be set to 1. If n modules are installed, it must be in the range 1:n. Not all the I/O modules installed in the target machine need to be used. To see how each I/O module maps to a Module ID, use this Speedgoat API: 

    speedgoat.getIoInterfaces("TargetName", "mySpeedgoat")
PCI Slot (-1: auto-search)

There are two approaches for mapping this block to a specific I/O module installed in your target machine. All modules of the same type must be configured using the same method.

  • Auto-Search: with the default value -1 the I/O module will be automatically located in the target machine. If you have multiple modules of the same kind, the Module ID defines which module is associated with this block. To see how each I/O module maps to a Module ID, use this Speedgoat API: 

    speedgoat.getIoInterfaces("TargetName", "mySpeedgoat")

  • Explicit Addressing: to explicitly define the logical address of the I/O module in the target machine, you can provide the PCI bus and slot numbers as a vector: [bus, slot]. To determine these numbers, run the following command in the MATLAB command window: 

    speedgoat.getIoInterfaces("TargetName", "mySpeedgoat", "Advanced", true)

    Note that the PCI address can change whenever an I/O module is added or removed – usually, auto-search is the best option.

Transceiver Setup

The electrical interface for each channel can be configured individually. The options are:

  • Disabled

  • RS-422 / RS-485

  • RS-423

  • RS-232

  • RS530 Mode (RS-422 / RS-423)

  • RS530A Mode (RS-422 / RS-423)

  • V.35 Mode (V.35 / RS-232)

Channel Setup Tab
Mode

Each channel can be configured individually to act as Data Communication Equipment (DCE) or as Data Terminating Equipment (DTE). This setting only affects the position and direction of the I/O pins.

Internal Clock Frequency

Each channel's clock can be individually configured. The Internal Clock Frequency always applies to both the receive and the transmit data lines RxD and TxD. A value of -1 indicates that an external clock is connected to the RxC input pins. A positive value defines the clock frequency to be generated by the module. The maximum value is 10e6 (10 MHz). The clock is available on the TxC pins.

Encoding

Selects binary encoding of Tx/Rx messages. The options are:

  • Not Encoded (NRZ)

  • Invert Polarity (NRZB)

  • NRZI-Mark

  • NRZI-Space

  • Biphase-Mark (FM1)

  • Biphase-Space (FM0)

  • Biphase-Level (Manchester)

  • Differential Biphase-Level

Max. Data Size

Defines the size of the data input from the Write block.

Underrun Response

Transmit underrun condition occurs if the transmitter needs another character to send but the TxFIFO is empty. The options are:

  • Abort (01111111)

  • Abort ('0' followed by 15 consecutive '1's)

  • Flag

  • Accumulated CRC followed by a Flag

Tx Idle

Define the Idle Line Condition:

  • Flags

  • Alternating Zeros and Ones

  • Continuous Zeros

  • Continuous Ones

  • Alternating Mark and Space

  • Continuous Space (TxD low)

  • Continuous Mark (TxD high)

Tx Parity

Select parity bit generation option:

  • No parity

  • Even

  • Odd

  • Zero (Space)

  • One (Mark)

Consecutive Flags Share Zero

Selects whether consecutive idle HDLC/SDLC Flags share a single intervening 0.

Tx Preamble Type

The transmitter sends the preamble sequence before sending the opening flag of each frame. The options are:

  • None

  • All Zeros

  • All Ones

  • All Flags

  • '101010...'

  • '010101...'

Preamble Length

Selects the length of the preamble.

Tx Character Length

The transmitter can format outgoing messages in packets of different length. You can select the packet length from a drop-down menu.

Tx CRC

Selects Tx CRC generation. The options are:

  • No CRC

  • 16-Bit CRC-CCITT

  • CRC-16

  • 32-Bit Ethernet CRC

Tx Clock Source

The transmitter can be clocked using either the internal programmable clock or using an external clock wired to the RxC pins of the corresponding channel. The options are:

  • RxC Input Pin

  • Internal Clock

Rx FIFO Interrupt Level

Defines the amount of data in the receive FIFO before an interrupts occurs. This then triggers the transfer of data from the hardware receive FIFO of the I/O module to the software FIFO.

Rx Software FIFO Size

The size of the receive software FIFO to buffer characters between interrupt service and periodic execution.

Rx Parity

Select parity bit checking option:

  • No parity

  • Even

  • Odd

  • Zero (Space)

  • One (Mark)

Rx Character Length

Selects how many bits the receiver assembles in each character.

Rx Address and Control Handling

  • No Address or Control field handling: The Receiver does not handle the Address or Control field. It simply divides all the data in all the frames received into characters per Rx character length and places the data in the RxFIFO.

  • 1-byte Address only: The Receiver checks the first 8 bits of each frame as an address. If they are all ones or if they match the contents of the Rx Sync value, the Receiver receives the frame into the RxFIFO, otherwise it ignores the frame through the next Flag. After placing the first 16 bits of the frame in the FIFO as two 8-bit bytes, the Receiver divides the rest of the frame into characters per Rx character length.

  • 1-byte Address, 1-byte Control: The Receiver checks an 8-bit address as described above. If these bits are all ones or if they match Rx Sync value, the Receiver places the first 24 bits of the frame in the RxFIFO as 3 8-bit bytes, before switching to dividing characters according to Rx character length.

  • 1-byte Address, 2-byte Control: The Receiver checks an 8-bit address as described above. If these bits are all ones or if they match Rx Sync value, the Receiver places the first 32 bits of the frame in the RxFIFO as 4 8-bit bytes, before switching to dividing characters according to Rx character length.

  • Extended Address, 1-byte Control: The Receiver processes an Extended Address at the start of each frame. First it checks the first 8 bits of the frame as described above. If these bits are all ones or if they match Rx Sync value, as the Receiver places each 8 bits of the address into the RxFIFO, it checks the LSBit of the 8. If the LSBit is 0, it goes on to place the next 8 bits into the RxFIFO as part of the address as well, through an address byte that has LSBit 1. Then, the Receiver places the next 16 bits of the frame into the RxFIFO as two 8-bit bytes, before switching to dividing characters according to Rx character length.

  • Extended Address, 2-byte Control: The Receiver processes an Extended Address as described above for Extended Address, 1-byte Control. If the first 8 bits of the address are all ones or if they match Rx Sync value, the Receiver places the 24 bits after the extended address into the RxFIFO as 3 8-bit bytes, before switching to dividing characters according to Rx character length.

  • Extended Address, Control >= 2 bytes: The Receiver processes an Extended Address as described above for Extended Address, 1-byte Control, and then an "Extended Control field". If the first 8 bits of the address are all ones or if they match Rx Sync value, the Receiver places the next 8 bits after the extended address in the RxFIFO without checking. Then, as the Receiver stores each subsequent 8 bits in the RxFIFO, it checks the MSBit of the 8 bits. If the MSBit is 1, it continues to receive more 8-bit bytes, through 1 byte that has its MSBit 0. Subsequently, the Receiver places one more 8-bit byte into the RxFIFO, before switching to dividing characters according to Rx character length.

  • Extended Address, Control >= 3 bytes: This mode differs from the one described above for Extended Address, Control >= 2 bytes, only in that the Receiver places the 16 bits after the extended address in the RxFIFO without checking, before starting to check MSBits for n nth end of the "extended Control field".

Rx Sync Value

8-bits unsigned comparison value for Address and Control handling (see above).

Rx CRC

Selects Rx CRC checking. The options are:

  • No CRC

  • 16-Bit CRC-CCITT

  • CRC-16

  • 32-Bit Ethernet CRC

Rx Clock Source

The receiver can be clocked using either the internal programmable clock or using an external clock wired to the RxC pins of the corresponding channel. The options are:

  • RxC Input Pin

  • Internal Clock

[Note]Note

When using the internal clock for the receiver, a DPLL is used to recover the receive clock. To keep the DPLL in sync, ensure the data signal contains enough transitions.

Disable Termination Resistor

For RS422/RS485, RS530, V.35, and RS422/RS423 Mixed Mode, the RxC, RxAuxC, and RxD have built-in termination at the transceivers. These internal terminations may be disabled to allow external terminations to be used. Selecting this checkbox will disable the internal transceiver termination resistors.