Documentation

This parameter associates a code module block with a configurable I/O module setup block. Set this value to match the Module ID defined in the setup block of the required configurable I/O module.

This box is only visible if your configuration file contains a code module that is using the analog inputs/outputs. If you want to use one of these analog code modules, you need to select the corresponding checkbox. The Analog setup block will then be automatically configured to support this analog code module. Parameters needing to be set to a specific value will be grayed out.

Analog input and output channels not reserved by an analog code module can still be used, but the channel group will be triggered by the code module. When the DMA interrupt is enabled, the whole channel group will be automatically disabled.

This checkbox selects between individual trigger settings per channel group or common trigger settings, which apply for all channels.

When this checkbox is selected, the Sample and Read mechanism is disabled. Due to the characteristics of the ADC chip, a sample is always transferred during the next acquisition, which makes it necessary to trigger twice (1: sample, 2: read) to obtain an immediate sample. In return, the maximum achievable sample rate is halved (2.5 Mbit/s). By default, this checkbox should be left disabled to obtain valid samples per trigger (especially for external triggers). Only when higher sample rates are required should this checkbox be enabled.

Four trigger options are available for the analog inputs depending on the settings defined for the Enable Individual Trigger Settings and Enable DMA Interrupt parameters:

Note: Due to the operating mechanism of the ADC on this module, each time a sample acquisition is triggered, the result of the previous acquisition triggered is returned. This means that at a regular rate of triggering, there will be a one trigger period latency for values returned from the ADC. This may be relevant for trigger modes where the exact timing of triggering is required, and where the sample rate is low (e.g., digital I/O triggering on the model sample rate). This delay is in addition to a model step delay introduced by the Read Value From Previous Model Step option, if selected.

At each model sample step the analog input data from the previous time step is read and a new transmission of the analog input channels is started, which will be read in the next model execution. Consequently, with this mode there is no active wait time during the data transfer to the CPU and the task execution time is lower.

This parameter is used to configure the internal sampling clock of the ADC.

This parameter is available if ADC Sample Trigger is set to I/O Module Internal Signal. A list of available internal trigger signals is shown in the drop-down menu. If no signal is available, then the selected configuration file does not include internal trigger signals; in this case choose a different trigger option.

This parameter is available if ADC Sample Trigger is set to I/O Module Digital I/O. Specify the digital I/O channel number to configure the corresponding signal as trigger signal. If the selected I/O line is configured as digital input in your model, an external signal can be connected for triggering. But the trigger signal routing also works for output signals and as well for code module functionality. For example if a digital line is configured as PWM-Trigger output signal, then the signal is also internally routed to the trigger input of the analog channels and can be used for triggering.

Select the oversampling configuration: none, 2, 4, 8, 16, 32 or 64. If oversampling is active, the I/O module takes the selected number of samples and averages them to one sample. In Frame-Based mode, only every nth sample is transferred over DMA. In Sample-Based mode, the filter acts as a moving average, and the CPU reads out the latest value.

The analog input data read back is organized in frames and can be synchronized using an interrupt. Either a triggered subsystem or the whole model can be executed based on the DMA interrupt. This checkbox is only visible, when Enable Individual Trigger Settings is disabled.

This parameter is shown if Enable DMA Interrupt is checked. The parameter is disabled and cannot be changed and only shows the applicable time resolution of the ADC trigger signal. The ADC sample time will be rounded to an integer multiple of the Trigger Resolution.

This parameter is available if Enable DMA Interrupt is checked. The ADC Sample Rate is used to configure the internal sampling clock, if Sample Trigger is set to I/O Module Clock. For the other ADC Trigger Settings it is used to calculate the expected block sample time.

This parameter is available if Enable DMA Interrupt is checked.

Select how many samples are transferred from the module at each CPU model step. The block port signal of every channel becomes a vector with the same number of values, where the value at position 1 is taken first. Enter "-1" to allow the system to determine the frame size automatically based on the ADC Sample Rate and the Input Block Sample Time.

This parameter is available if Enable DMA Interrupt is checked.

Define the base sample time at which the Analog input interrupt gets asserted. Enter "-1" to allow the system to determine the block sample time automatically based on the ADC Sample Rate and Frame Size.

The block supports four trigger options for the analog outputs:

This parameter is available if DAC Sample Trigger is set to I/O Module Internal Signal. A list of available internal trigger signals is shown in the drop-down menu. If no signal is available, then the selected configuration file does not include internal trigger signals; in this case choose a different trigger option.

This parameter is available if DAC Sample Trigger is set to I/O Module Digital I/O. Specify the digital I/O channel number to configure the corresponding signal as a trigger signal. If the selected I/O line is configured as a digital input in your model, an external signal can be connected for triggering. But the trigger signal routing also works for output signals and also for code module functionality. For example, if a digital line is configured as a PWM-Trigger output signal, then the signal is also internally routed to the trigger input of the analog channels and can be used for triggering.

The analog output data is written to the I/O module and synchronized using an interrupt to ensure continuous data. Either a triggered subsystem or the whole model can be executed based on the DMA interrupt.

This parameter is available if Enable DMA Interrupt is checked. The FIFO Threshold determines when the interrupt is asserted to request new data from the CPU; this means that the interrupt is asserted as soon as only FIFO Threshold samples/channel remain. The threshold should be chosen such that enough samples are still in the FIFO to output on the DAC, while new data is requested and received from the CPU (this includes: trigger interrupt time, execution of CPU model step, DMA data transfer). The FIFO Threshold value must be equal to or less than the Frame Size value.

This parameter is shown if Enable DMA Interrupt is checked. The parameter is disabled and cannot be changed and only shows the applicable time resolution of the DAC trigger signal. The DAC sample time will be rounded to an integer multiple of the trigger resolution.

This parameter is available if Enable DMA Interrupt is checked. The DAC Sample Rate is used to configure the internal sampling clock, if Sample Trigger is set to I/O Module Clock; otherwise it is used to calculate the expected block sample time.

This parameter is available if Enable DMA Interrupt is checked.

Select how many samples are transferred to the module at each sample hit. The block port signal of every channel becomes a vector with the same number of values, where the value at position 1 is taken first. Enter "-1" to allow the system to determine the frame size automatically based on the DAC Sample Rate and Frame Size.

This parameter is available if Enable DMA Interrupt is checked.

Define the base sample time at which the Analog output interrupt gets asserted. Enter "-1" to allow the system to determine the block sample time automatically based on the DAC Sample Rate and Frame Size.

Choose the active input channels by selecting the corresponding checkboxes. The board has 32 differential input channels. The channels can be enabled individually. The voltage range is ±10 V. The corresponding channels will be automatically enabled for all the code module functionalities selected. Groups of analog input channels which contain an active analog code module input are excluded from the DMA stream when the Enable DMA Interrupt checkbox is selected.

Choose the active output channels by selecting the corresponding checkboxes. For each active channel, a separate row for the channel settings is displayed. For all the enabled code module functionalities, the corresponding channels will be automatically enabled.

±2.5 V, ±5 V, ±10 V,

Define the initial signal level present on the specific output after the application has been downloaded. The values can be set individually by entering the initial value for each channel according to the selected output range.

Define whether the initial value is also applied once the application has stopped. The behavior can be set individually for each channel using the checkbox.