Documentation

There are two approaches for mapping this block to a specific I/O module installed in your target machine. All modules of the same type must be configured using the same method.

The Module ID has two functions:

This setting is only available if the Analog input or Analog output block uses DMA.

The clock base rate is used by the two clock dividers for conversion clocks 1 and 2; for example, if the clock base rate is set to 20 MHz and the clock divider is set to 1000, the resulting conversion clock is 20 kHz. On this basis, a new sample is generated or converted every 50 μs. Note that the maximum data acquisition rate of 800 kSPS is only achievable if one channel per Input Group is active. If two channels per input group are active, the maximum achievable rate is 400 kSPS.

This setting is only available if the Analog input or Analog output block uses DMA.

The IO141 I/O module has two different conversion clocks which can be used by the Analog input or Analog output blocks during DMA operation. During normal operation, the Simulink model triggers each conversion, but during DMA operation, the hardware does this independently from the model and therefore needs a clock. For more information refer to the description of the clock base rate.

This setting is only available if the Analog input or Analog output block uses DMA.

It enables the frame trigger, which starts the conversion of a new analog data frame at a configurable rate. For more information refer to the usage notes.

This setting is only available if the Analog input or Analog output block uses DMA and the frame trigger has been enabled.

It defines the frame trigger rate. One of the conversion clocks acts as the source for the frame trigger. All the blocks using DMA must use the same conversion clock. The frame trigger will choose the appropriate clock.

As the frame trigger uses a fraction of the conversion clock, the maximum frame size is equal to the divider; for example, if the frame trigger clock divider has a value of 100, then the analog input frame size can be between 1 and 100 samples.

Select the input coupling mode for each input group: Differential or Single-Ended

This indicates the available channels per input group, which can be activated depending on the chosen input coupling mode.

Differential mode: ±0.64 V, ±1.28 V, ±2.56 V, ±5.12 V, ±10.24 V, ±20.48 V, and ±24.576 V

Single-ended mode: ±0.64 V, ±1.28 V, ±2.56 V, ±5.12 V, ±10.24 V, and ±12.288 V

The chosen voltage range will apply to all channels within the same input group.

Enable individual voltage range selection per channel for each input group.

Enable or disable the data correction. When enabled, the factory calibrated onboard correction values are used to correct every analog-to-digital conversion.

This setting enables incoming data to be transferred over DMA. It also allows much higher system sampling rates to be achieved as the CPU does not have to process the data transfer. In addition, frame-based operation is possible, meaning that multiple samples can be received from the I/O module in one sample hit. If DMA is enabled, the model or subsystem containing the Analog input block must be triggered with the I/O module DMA interrupt for consistent results. Refer to the usage notes for information on configuring DMA.

Select which clock is used to start the conversion of a new sample. The frequency of the clocks can be changed in the main tab.

Select how many samples are transferred from the module at each sample hit. The block output of every channel becomes a vector with the same number of values, where the value at position 1 is taken first. Enter "-1" to allow the system to determine the frame size automatically based on the conversion clock and input block sample time.

Either the frame size or the input block sample time must be configured automatically (-1).

Define the base sample time at which the Analog input block gets its sample hit. Enter "-1" to allow the system to determine the input block sample time automatically based on the conversion clock and frame size.

Either the frame size or the input block sample time must be configured automatically (-1).

Choose the active input/output channels by selecting the corresponding checkboxes. For each active channel, a separate row for the channel settings is displayed.

Select the voltage range for every output channel: 0-5 V, 0-6 V, 0-10 V, 0-12 V, ±5 V, ±6 V, ±10 V or ±12 V or select the current range for each output channel: 4-20 mA, 0-20 mA, 0-24 mA.

Define the initial signal level present on the specific output after the application has been downloaded. The values can be set individually by entering the initial value for each channel according to the selected output range.

Define whether the initial value is also applied once the application has stopped. The behavior can be set individually for each channel using the checkbox.

Enable or disable the data correction. When enabled, the factory calibrated onboard correction values are used to correct every digital-to-analog conversion.

Enable or disable the simultaneous channel update. When enabled, all the analog outputs are updated simultaneously. This increases the task execution time, as the module waits for all the data to be transferred from every active channel before initiating the analog output update. When disabled, each channel is updated immediately after the data transfer.

This setting enables outgoing data to be transferred over DMA. Frame-based operation is possible, meaning that multiple samples can be transferred in one sample hit. If DMA is enabled, the model or subsystem containing the Analog output block must be triggered with the I/O module DMA interrupt for consistent results. Refer to the usage notes for information on configuring DMA.

Select the latency between the sample hit and the actual conversion at the output. The available options are As small as possible or Until next frame. If As small as possible is selected, the values will appear at the module outputs shortly after the block sample hit. However, the latency will not be constant, which might lead to lags at the output. If Until next frame is selected, then the module starts to output the data at the next block sample hit. This ensures a constant latency and enables a continuous data output. This is especially useful when both the analog input and output use DMA. Refer to the usage notes for more information on this topic.

Select which clock is used to start the conversion of a new sample. The frequency of the clocks can be changed in the main tab.

Select how many samples are transferred to the module at each sample hit. The block input of every channel becomes a vector with the same number of values, where the value at position 1 will be converted first. Enter "-1" to allow the system to determine the frame size automatically based on the conversion clock and output block sample time.

Either the frame size or the output block sample time must be configured automatically (-1).

Define the base sample time at which the Analog output block gets its sample hit. Enter "-1" to allow the system to determine the output block sample time automatically based on the conversion clock and frame size.

Either the frame size or the output block sample time must be configured automatically (-1).

Enable or disable the debounce filter to eliminate any switch bouncing on the digital inputs. When enabled, the Debounce Filter Time field appears where you can specify the required value.

Specify the middle of the two debounce filter times you require, where T_pass is always 1.5 times the value of T_reject. Pulses with a duration smaller than T_reject are filtered and are not passed on to the internal logic. After an input pin performs a rising or a falling edge, T_pass defines how long this new logic level must be stable before the level change is passed on to the internal logic. Please note that pulses with a duration between T_reject and T_pass may or may not be filtered. T_reject can be configured between 50 ns and 3.2768 ms. T_pass can be configured between 75 ns and 4.9152 ms.

Select the reference voltage of the pull resistor for the front I/O: Floating, Weak pull-up 5 V, Pull-up 3.3 V or Pull-down. Note: if Floating is selected, the pull resistors will not be connected to a reference level, but they will still nonetheless be connected to each other. If Weak pull-up 5 V is selected, the external load current cannot exceed 250 µA in order to achieve a valid CMOS high level.

Digital I/O Output Circuit: